1. Field of the Invention
The present invention relates to a dynamic type semiconductor memory device, and more particularly to, a dynamic type semiconductor memory device including dummy cells capable of accurately reading information from a memory cell array.
2. Description of the Related Art
FIG. 6 shows an equivalent circuit of a memory cell of a dynamic type random access memory device (DRAM). In the equivalent circuit shown, reference numerals 61 and 62 show a MOS transistor for transfer gate and a capacitor for information storage, respectively. The MOS transistor 61 has a drain connected to a bit line 63, a gate connected to a word line 64 and a source connected to one terminal of the capacitor 62. The other terminal of the capacitor is connected to a predetermined potential.
In the dynamic type memory cell, a voltage is applied to the bit line 63 and word line 64 at a time of writing to turn the transistor 61 ON. When this occurs, an electric charge moves through the bit line 63 to the capacitor 62 where it is stored. At a time of reading, a voltage is applied to the word line 64 to allow the electric charge to be released via the transistor 61.
Thus, the performance of the memory cell is substantially determined by the characteristics of the transistor 61 and the capacitor 62. In order to retain the electric charge in good condition, it is necessary to suppress the leak level of the charge, but it is important that a quantity of charge stored in the capacitor 62 be increased.
On a cross-sectional structure of a conventional dynamic memory cell, two memory cells adjacent to each other will be described.
FIG. 7 shows the cross-sectional structure of a planar capacitor type memory cell array having a charge storage region in a surface of a semiconductor substrate. That is, an isolation region 72 is selectively provided in, for example, a P-type semiconductor substrate 71. A source region 73 and a drain region 74 for a transfer gate transistor, which are comprised of an opposite conductivity type diffused layer (N.sup.+ -type), are provided in the isolated substrate 71. A charge storage region 75 is formed in the substrate so as to be continuous with the source region 73 and serves as one electrode of capacitor. An electrode plate 77 is provided above the substrate through an insulating film 76. The electrode plate 77 serves as the other electrode of the capacitor. A gate electrode (word line) 79 for the transfer gate transistor is provided between the source region 73 and the drain region 74 through a gate insulating film 78. A bit line, not shown, is in contact with the drain region 74.
Recently, with demand for high density DRAMs, there have been used a trench capacitor type memory cell as shown in FIG. 8 and a stocked capacitor type memory cell as shown in FIG. 9. In the trench capacitor type memory cell as shown in FIG. 8, a charge storage region 83 is provided in an inner surface of a trench 82 formed in a semiconductor substrate 81. The charge storage region 83 is formed of a diffused layer whose conductivity type is opposite to the semiconductor substrate. In the structure, the other parts or portions of the memory cell are the same as those shown in FIG. 7 and are shown with identical reference numerals used for them. In the stacked capacitor type memory cell shown in FIG. 9, a charge storage region 92 of polysilicon is provided above a gate electrode (word line) 79, an isolation region 72, etc., through an interlevel insulator 91, and is in contact with a source region 73. The other parts or portions of the memory cell are the same as those shown in FIG. 7 with identical reference numericals employed for them.
In the trench and stacked capacitor type memory cells, it is possible to provide a charge storage region having the same area on the reduced substrate surface area, as compared to the planar capacitor type memory cell. In relation to the memory capacitance, a memory cell having the same storage performance can be provided on a smaller substrate surface area, assuring a high density memory cell array.
In a conventional DRAM memory cell array, memory cells of the same type are adjacently arranged on a substrate so as to provide a matrix of memory cells as schematically shown in FIG. 10. Considering both electrical connections among memory cells and common bit and word lines BL, WL and the high density arrangement, memory cells may be located in such a manner that their capacitor (each charge storage region is marked with "C") of adjacent memory cells are arranged in close proximity. In FIG. 10. a transfer gate transistor and a contact between the drain of the transfer gate transistor and the bit line BL are represented by "G" and ".cndot." respectively.
The high density of the conventional memory cell array has been achieved by primarily modifying a memory cell array structure, but there has been required for an increasing demand for a higher integration density structure and hence a memory cell array structure with memory cells arranged more closely adjacent one another. Since, in the conventional memory cell array, the adjacent capacitors of the memory cells are adjacent to each other as described above, charge storage regions formed above a common substrate or a common conductive film may be arranged in proximity. In the memory cell array, it may be a key to reduce the distance between memory cells, that is, to locate the charge storage regions in close proximity.
Depending upon the limit of finely patterning a film as well as mutual transfer of the charge (destruction of stored data) caused by a proximity effect between the charge storage regions, the distance between the charge storage regions is given by at least 0.5 .mu.m or more. That is, a limited condition may occur against the arrangement of the memory cells, thereby interrupting the increase in the integration density of the memory cell array. In this case, "the limit of finely patterning the film" means a minimum dimension capable of patterning a single film. The "proximity effect" between the charge storage regions represents an action of electric charge which passes through the substrate in the planar and trench capacitor type memory cells and through the interlevel insulator in the stacked capacitor type memory cells to move between charge storage regions. The effect is prominent for the trench capacitor type memory cell in particular.
A DRAM for satisfying the aforementioned requirement has already been proposed by Japanese Patent Application No. 62-227307 (Published Unexamined Japanese Patent Application No. 64-69049). As shown in FIG. 11 or 12, the memory cell array of the DRAM includes first memory cells (marked with "o") each having a shallow diffusion layer as a cell node and second memory cells (marked with "x") each having a deep diffusion layer as a cell node. These first and second memory cells are arranged in such a manner that the cell nodes of the second memory cells are not adjacent to each other through a field insulating film. In this case, the memory cells are arranged on the substrate to provide a matrix. However, in the memory cell array shown in FIG. 11, different kinds of memory cells are alternately arranged in a direction of a common bit line BL. In FIG. 11, WL represents a direction of a word line, and CT represents a contact between the bit line and a memory cell transistor, respectively.
According to the arrangement, since leak current in a pseudo MOS transistor, which uses the field insulating film as a gate insulating film, is small, it is possible to arrange the adjacent memory cells in proximity. Therefore, the integration density of such a memory cell array can be increased because the occupation of the cell area is made small which is a feature of the second memory cells.
In the case where different kinds of memory cells are connected to the common bit line, the bit line potentials may be different from each other when the same data is read from the first and second memory cells connected to the same bit line, because they have the different capacitance values due to the different charge storage regions. Accordingly, when the data is read from the different memory cells, it cannot be possible to accurately detect the information.